Line driver circuits are used to translate digital data into an analog waveform on a wire or antenna. In many instances, the output of the line driver circuit generates a voltage corresponding to the digital data. A common line driver circuit is shown in FIG. 1.
Transistors 2a and 2f regulate the total amount of current in the circuit as dictated by bias voltages Bias P and Bias N. Raising or lowering Bias P and Bias N increases or decreases the amount of total current flowing through the other 4 transistors, 2b, 2c, 2d and 2e. 
Transistors 2b, 2c, 2d, and 2e are controlled by voltages Pn, Pp, Nn, and Np. These voltages are applied selectively to route current from the bias sources from node Zp towards node Zn or from node Zn to node Zp. When Pn and Np are asserted, transistors 2b and 2e are ON. At the same time, Pp and Nn are deasserted and transistors 2c and 2d are OFF. The current from bias source 2a is routed down through 2b, across 4a, across 4b, down through 2e and then down through 2f. Voltage measured across Zp-Zn will result in a positive value.
Conversely, when Pp and Nn are asserted, transistors 2c and 2d are ON. At the same time, Pn and Np are deasserted and transistors 2b and 2e are OFF. The current from bias source 2a is routed down through 2c, across 4b, across 4a, down 2d and then down through 2f. Voltage measured across Zp-Zn will result in a negative value.
Headroom is defined as the required potential difference between voltage supplies Vdd and Vss. Because each transistor requires a minimum voltage across its source and drain, stacking transistors requires a minimum headroom. For the example shown in FIG. 1, there are 4 transistors, {2a, 2b, 2e, 2f} or {2a, 2c, 2d, 2f} between Vdd and Vss.
Output swing is defined as the voltage swing between the output nodes. For example, in FIG. 1, the output nodes are defined as Zp and Zn. The current passing through elements 4a and 4b determines the voltage across Zp and Zn. The exact voltage is determined by the amount of current and the value of elements 4a and 4b. 
Common mode voltage is defined as the average voltage between two nodes. For the circuit illustrated in FIG. 1 it is the average voltage between the output nodes Zp and Zn. Because elements 4a and 4b are matched, voltage between them can be considered the common mode voltage.